On the compact modelling of Si nanowire and Si nanosheet MOSFETs

Scalability of FinFETs and Unstrained–Si/Strained–Si FDSOI–MOSFETs

Full–band Monte Carlo simulations are performed for n–type FinFETs as well as for unstrained–Si and strained–Si fully–depleted (FD) SOI–MOSFETs. Gate lengths of 50 nm down to 10 nm are considered, and a fixed off–current of 100 nA/μm is in each case ensured by adjusting the silicon film thickness. The FinFET shows the best scaling trend, but the strained–Si FDSOI–MOSFET always involves the larg...

Strained-Si single-gate versus unstrained-Si double-gate MOSFETs

Self-consistent full-band Monte Carlo simulations are employed to compare the performance of nanoscale strained-Si single-gate (SG) and unstrained-Si double-gate (DG) MOSFETs for a gate length of 25 nm. Almost the same on-current as in the DG-MOSFET can be achieved by strain in a SG-MOSFET for the same gate overdrive. This is due to the compensation of the higher electron sheet density in the t...

Scaling Of Si MOSFETs For Digital Applications

Diffusion in Si(x)Ge(1-x)/Si nanowire heterostructures.

Si0.48Ge0.52/Si tip/nanowire heterostructures were grown by pulsed laser vaporization (PLV) at a growth temperature of 1100 degrees C. Ge diffusion in [111]-growth Si nanowires was studied for different post-synthesis annealing temperatures from 200 degrees C to 800 degrees C. Ge composition profiles were quantified by energy-dispersive X-ray spectroscopy in a transmission electron microscope. ...

Transport in Thin-Body MOSFETs Fabricated in Strained Si and Strained Si/SiGe Heterostructures on Insulator

The combination of channel mobility enhancement techniques such as strain engineering, with non-classical MOS device architectures, such as ultra-thin body or multiple-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future CMOS technology nodes. Two structures that combine strain engineering an...